For VLSI chips implemented in deep sub-micron process technology (less than 0.25 micrometer), die-to-die and intra-die variations can cause significant degradation in chip performance. In most applications, chips are both power and timing constrained, causing a situation where any deviation from the typical process may lead to a loss in yield. Any transistor that operates near the slow end of the process range causes the frequency of the chip to suffer. Any transistor operates near the fast end of the process range causes the chip power consumption to increase. In a chip with tight power and frequency constraints, this may lead to many chips being discarded. Ideally, the designer wants all transistors in a chip and all chips in a wafer to behave the same and to behave in a typical fashion. The fast end of the range was not previously a problem, since leakage current was not an issue in larger geometries. Now, with leakage current being a significant portion of the on-chip power, any variation in leakage power can cause the chip to fail its power budget.
Supply voltage adjustment has been used to control chip operation. It is known that both power and speed scale with supply voltage. In particular, power increases as the square of the supply voltage. In addition, it is also known that N-well and P-well biasing of the integrated circuit affects leakage current and speed. However in the prior art, power supply adjustment and well biasing adjustment have been done on a per-chip basis. Using this approach, it may be impossible to bring a chip within power and speed constraints.
Accordingly, there is a need for improved methods and devices for enhancing the operation of integrated circuits.